The present invention relates generally to the field of integrated circuit (IC) physical design, and more particularly to circuit element congestion reduction.
During the physical design stage of integrated circuit design, electronic design automation (EDA) tools place and optimize the electrical components and interconnections planned during the logical design phase. EDA tools generate possible locations for the electrical components based on various factors including the size of the circuit, the locations of various child blocks within a parent block, and timing requirements. Once placement completes, a global routing tool, which may be a function of the EDA tool, generates a layout for the electrical interconnections (nets) that complete the circuit by connecting all of the electrical components according to the logical design of the circuit.
Each net in the circuit follows a path through one or more conducting layers in the IC design. Nets can be modified in order to satisfy functional requirements of the circuit design, such as timing requirements. One method of modifying the nets is to “promote” or “demote” the net, or a subnet of the net. When a net is promoted or demoted, the net is physically relocated from one layer to another in a stack of conducting layers on which the nets are formed. Different layers allow for different signal transmission times in the wires. Typically, higher layers allow for faster signal transit times and lower layers allow for slower signal transit times. Another method of changing signal transit times is by modifying the width, or “wire-code” of the net. In this method, the cross-sectional area of the net is increased or decreased to allow for faster or slower signal transit times, respectively. As used herein, the term “slack” refers to the difference between the required signal transit time and the actual signal transit time (as specified in the functional requirements of the circuit design).